Inverter Turn-On

TM 11-6125-25930

output Z604-4 only ensures that latch Z605-6 will

state. The latch circuit is now ready for the next

remain at high as explained below). The high pulse

overcurrent condition. Also, with the low now at

at Z604-13 goes to nand gate input Z605-10 along

latch output Z605-6, the cathode ofCR609 is at low

which turns on transistor Q606 and then transistor

with the high at input Z605-9 from the latch. Nand

gate output Z605-8 is then set to low by the two

Q607, which in turn shorts out capacitor C611

highs and this low, finally, causes a low at nand gate

setting negative input Z601-8 of comparator at low

output Z608-6 which turns off all inverter output

causing comparator output Z601-14 to go to its

normal high level.

current by setting major bridge logic signals

to low for 1.5 seconds. The absence of

d. Inverter Turn-On. When the inverter is initially

through

current for 1.5 seconds puts a low at nand gate

turned on, protective logic circuits are employed to

input Z605-13 which sets timer input Z604-1 to

hold off operation of several sections of the inverter

high. After the 1.5 second, when the major bridge

until other sections are operative.

through

and inverter output

logic outputs

(1) Protective delay of inverter output voltage

current is enabled again, if an overcurrent condition

and 37 vdc boost voltage for first second after turn-

is still present, then nand gate input Z605-13 will go

on. Timer Z604-10 input (see figure FO 2-2, sheet 2)

back to high, setting output Z205-11 back to low

is triggered by a low-high transient due to capacitor

C604 charging up to a high from the high level at

(other input Z605-12 is still held at high by latch

Z605-6). This sequence of high-low at timer input

comparator output Z601-1. Timer output Z604-5

Z604-1 triggers the timer again and another 1.5

now delivers a on-second high pulse to the anode of

diode CR607 causing transistor Q605 to turn on

second high pulse is sent out at timer output

which sets the transistor Q605 to low.

Z604-13. This pulse again shuts off all inverter

This low at schematic point to figure FO 2-2,

output current for 1.5 seconds. However, afer the

1.5 seconds, if at this time the overcurrent condition

sheet 1, inhibits the 37 vdc boost voltage from

is removed, then nand gate input Z605-13 will

turning on (as described above in the case of an

remain at low and timer input Z604-1 will not be

overvltage condition) and also goes to rand gate

triggered and thus the inverter output current will

input Z-608-12 to put a high at vrom Z602-15 chip

enable input which holds all major and minor bridge

not be shut off. The absence of he overcurrent

)

through

condition also sets comparator output Z601-1 to

logic outputs (schematic points

at low so that inverter output voltage is cut off. The

high Which goes to prom input Z602-14 and restores

the prom to program the normal quasi sine

low at collector of transistor Q605 also directly

waveform at major bridge logic outputs

holds major bridge logic output schematic points

at low and minor bridge logic

; and also restores normal minor bridge

through

. The inverter is now

, and at low

through

output schematic points

outputs

restored to its normal condition except that latch

by controlling the nine associated nand gates. This

output Z605-6 is still latched at high; if it remained

delay is inverter output voltage allows the 9.6 kHz

latched then if another overcurrent condition oc-

oscillator counter and prom circuits time to

stabilize. Also, note that the inverter 37 vdc supply

cured then timer Z604-1 input would be triggered at

can still build up enough power to supply energy to

once rather than five seconds after the overcurrent

condition. Therefore, the latch is reset as follows.

the +15, vdc supply even though the 37 vdc boost

regulation circuit has been temporarily held off.

when inverter has no overcurrent condition then

(2) Protective delay of +5 vdc supply, inverter

timer Z604-1 input is no longer triggered and timer

output voltage and 37 V boost voltage until +15 vc

Z604-4 output remains at its normal high level

supply has reached a minimum of 13 volts. Im-

(during overrcurrent condition Z604-4 outputs a low

pulse every few seconds); this high level puts a long

mediately after turn-on of inverter before +15 vdc

supply has reached 13 Volts, comparator positive

term high at the cathode of diode CR610. The

input Z601-11 which sees the +15 volt supply will

cathode of diode CR609 is also at high due to the

high at nand gate latch Z605-6 output. The two

be low in relation to input pin 10 zener diode CR603

highs allow the normal condition of a high at the

reference, and Z601-13 output will thus be low. This

base of transistor Q606 which turns it off and causes

low turns on transistor Q604 puttin a high at the

transistor Q607 to turn off.Capacitor C611 can now

anode of CR68 which turns on transistor

charge up in about seven seconds to a high that sets

Q605, resulting in a low at collector of transistor

comparator Z601-14 output to low. This low goes to

Q605. This low holds off inverter output power

(as

through

nand gate input Z605-1 which causes a high at latch

through logic outputs

described above) and also holds off turn-on of 37 volt

input Z605-4 which in turn sets latch output

Z605-6 to low because latch input Z605-5 is high

boost regulator through low signal at schematic

point

due to timer Z606 being in its normal, untriggered

which goes to boost circuit (as described

2-6