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TM 11-6130-429-40
the voltage on pin 9 is reduced, the pulse width nar-
(2) The voltage regulator operates from the fil-
tered Dc input and delivers regulated 17 VDC to the
rows and reaches zero at approximately 2V on pin 9.
(6) Resistor R26 applies 5V to "pull up" pin 9,
primary control circuits. The filtered input voltage is
creating maximum pulse width and hence, maximum
applied through resistor R1 to generate an 8V refer-
output voltage from the switching power supply. Pin
ence across zener diode VR1. Transistor Q2 turns on,
9 is pulled down through R20 by light-coupled tran-
thereby turning on transistor Q1, and the output
sistor U6, which in turn is activated by the voltage
voltage of the regulator rises towards a nominal 17V
regulating circuits described previously. Accord-
as measured across C1. When the output voltage
ingly, when the output voltage reaches the desired
reaches approximately 17V, zener diode VR2 con-
level, U6 turns on, thereby reducing the voltage on
ducts, thereby raising the voltage on the emitter of
pin 9 to achieve the desired regulated output.
Q2, which limits the drive to the regulator loop to
(7) Capacitor C4 and resistor R19 limit the speed
maintain the output voltage constant, independent
with which the voltage on pin 9 may be changed, and
of line and load condition.
in effect, determine the transient response and the
(3) U7 is part of the undervoltage light-coupled
stability (no oscillations) of the power supply.
transistor described previously. In the event of an
(8) When power is first applied to U1, a slow
undervoltage condition, U7 turns off, thereby turn-
conversion from a very narrow pulse to the desired
ing on Q4, which turns on Q3 and activates the front
pulse width takes place so that the power supply
panel FAULT light.
builds up in a controlled manner and avoids unneces-
(4) U1 contains all of the basic components nec-
sary transients. Upon turn on, C5 is discharged and
essary to drive a pulse width modulated DC-DC con-
charges up through CR4, thereby controlling the
verter. The chip is activated by applying regulated
pulse width during the turn on interval and generat-
17V to pin 15. Pin 16 is an internal 5V reference, and
ing the soft start desired.
terminals 1 and 2 are an input operational amplifier
which can be used to control the output pulse width.
h. Drive Circuits (fig. 1-8).
It is not used in this case and resistive divider
(1) Internal transistors from 10 to 11 and from
R7-R8-R9, in effect, makes it nonoperational. The
12 to 13 in U1 are turned on when the pulse is gener-
chip generates pulse width modulated outputs as
ated. The control voltage is applied through resistor
indicated on pins 14 and 15. The outputs are 180 out
R11 to pins 11 and 12, thereby activating these tran-
of phase and operate at 20 kHz. These outputs are
sistor circuits. When the transistor from pins 10 to
used to drive the switching transistors in the DC-DC
11 is turned on, a positive pulse is generated on the
emitter of transistor Q5, driving it positive and caus-
(5) The 20 kHz is generated inside the chip by
ing it to conduct by the amount determined by R11.
dividing a 40 kHz clock by two. The frequency of the
The collector of Q5 goes positive, thereby activating
clock is determined by R15 and C3. Pin 9 is a compar-
Q7 and driving the base of power inverter transistor
ator circuit which determines the duty cycle or pulse
Q1 to the on position. Resistor R12 limits the drive to
width delivered from pins 11 and 14. When the volt-
the base of Q17 and R16 determines the current sup-
age on pin 9 is approximately at 4V, the pulses are at
plied to Q1.
maximum width (approximately 50% duty cycle). As

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