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TM 11-6130-429-40
age. When the output voltage before the diodes
(2) CR10 and CR11 are the coasting diodes
reaches the predetermined maximum, the light-
through which the current from choke L3 passes
coupled transistor is turned on, which in turn nar-
during the off position of the cycle. The RC networks
rows the pulse width and limits the maximum volt-
across each rectifier are commutation networks to
age. This assures a minimum standby voltage when
minimize noise and to protect the Schottky rectifiers
the power supply is operating in the standby "redun-
from transient spikes. Choke L3, in conjunction with
dant" mode.
output capacitors C14 and C15, acts as a low pass
(2) The output voltage at P1 and P2 is moni-
filter to eliminate the AC components and only pass
tored by separate error amplifiers which compare
the DC to the output; i.e., the DC is smoothed by the
these output voltages with the same reference. In the
filtering process. Capacitors C12, C13, and C17 and
event that the output voltage at one of the connec-
common mode choke L4 act as a common mode filter.
tors is below preset minimum, the error amplifier will
(3) Diode steering to P1 is provided by CR20,
override the monitor amplifier and turn off the light-
CR12, and CR13 operating in parallel. The output
coupled transistor, thereby widening the pulse width
voltage prior to the diodes is monitored by resistor-
until the desired output voltage at the connector is
protected test point TP2 and the output voltage af-
ter the diodes is monitored by resistor-protected test
(3) The desired output and monitor voltages are
point TP4. The output voltage is steered to P2
set by changing the common voltage reference, and
through CR21, CR14, and CR15, and the output volt-
accordingly, the monitor on the two connectors out-
age at the connector is monitored by resistor-
puts will be set to the same voltage by the single
protected test point TP3.
adjustment. The monitor voltage comparator (before
(4) The return is connected to P1 and P2 and is
monitored by test point TP1. Capacitors C19 and
the diodes) is set at approximately 0.3V higher than
the desired output voltage at the connector which
C20 are utilized for "despiking" the output after the
compensates for the redundant diode drop in the near
redundant rectifiers.
no load condition.
d. Secondary Regulator and Control Circuits.
e. Regulator Loop (fig. 1-5).
(1) The secondary regulator circuit monitors the
voltage before the redundant diodes and on the out-
put terminals of P1 and P2. An internal voltage refer-
Redundant diodes and output connectors
ence is generated. This is compared with the above
are shown in simplified form. The regula-
voltages by three separate comparators whose out-
tor components shown within the dashed
puts are collated and, in turn, activate a light-coupled
lines are part of PCB A1, with the excep-
transistor which controls the pulse width generator
tion of the +5V monitor voltage adjust
in the DC-DC converter. When the light-coupled
which is on the front panel.
transistor is in the off condition, the pulser is turned
"full on", thereby generating maximum output volt-

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