Quantcast Power Supply Circuit.


Click here to make tpub.com your Home Page

Page Title: Power Supply Circuit.
Back | Up | Next

Click here for thousands of PDF manuals




Information Categories
.... Administration
Food and Cooking
Nuclear Fundamentals


Share on Google+Share on FacebookShare on LinkedInShare on TwitterShare on DiggShare on Stumble Upon
Figure 5-2.1. Inverter drive A1A2 overall block figure diagram, 1974 model.
TM-11-6130-377-14 Inverter Power Static PP-7078/U Manual
Quarter-Start Generator.
TM 11-6130-377-14
(2)  Parallel SCR driver input.
When the
(2)  When the system input circuit breaker is
turned on, +120 vdc input voltage is applied to the
inverter is connected for parallel operation of two units, a
inverter drive circuit board. Upon receipt of the +120 vdc
cable is connected between connector P2 of the master
input voltage, the power-on delay circuit inhibits the
inverter drive circuit board and connector P2 of the slave
voltage fault sensors through the sensor delay, and
inverter drive circuit board. Connector P2 on the master
inhibits the SCR drive. After 2 to 5 seconds, the power-on
inverted contains the same jumpers as used for non-
delay circuit times out and initiates the sensor delay
parallel operation, so that the SCR driver is operated from
(which continues to inhibit the voltage fault sensors), and
its own oscillator and frequency divider, in addition to
initiates the quarter-start generator. After a further delay
interconnecting wires to the slave inverter. Connector P2
of approximately 50 milli-seconds, the sensor delay
on the slave inverter, however, does not contain jumpers
removes the inhibit command from the voltage fault
on its connector P2 pins 7 to 8, 3 to 10, 2 to 11, and 6 to
12.  Instead, the SCR driver of the slave inverter is
operated from the oscillator and frequency divider of the
(3)  The +120 vdc input voltage is monitored by
master inverter through the cable so that both inverters
the voltage fault sensors. If the voltage of the input drops
are operated in phase with each other. Master inverter
to approximately 95 vdc or rises to approximately 142
connector P2 pins 7, 10, 11, and 12 are connected
vdc, the appropriate voltage fault sensor causes the shunt
through the cable to slave inverter connector P2 pins 7,
trip driver to energize the shunt trip coil of the inverter
10, 11, and 12, respectively.  Other connections to
input circuit breaker (not on the circuit board) and
connector P2 during parallel operation are described in
disconnects the inverter from the +120 vdc input voltage.
the parallel sensor interconnection description (para 5-
Normal operation is restored by correcting the voltage
fault and resetting the input circuit breaker.
(3)  SCR driver circuit. The SCR driver consists
b. Power Supply Circuit. Referring to the detailed
of phase-splitter U4 and transistors Q4 and Q5. The 60-
schematic diagram of the inverter drive circuit board (fig.
Hz input to transistor Q5 is inverted by one gate and the
FO-2), the power supply consists of regulator U5 and filter
input to transistor Q4 is double-inverted by two gates of
capacitors C12, C18, C19, and C20. The regulator starts
integrate circuit U4, which is connected as a phase
operating when dc input power is first applied to the
The complementary 60-Hz signals cause
system. Shunt regulator Q6 and CR3 reduces the input
transistors Q4 and Q5 to drive output transformer T1.
voltage to +10 to +12 volts at connector J1 pin 10 to a
Transformer T1 provides gate drive for the inverter power
regulated +5 vdc level that is filtered for use by the low-
SCR's through resistor diode network R13, R14, R15 and
level circuitry of the inverter drive circuit board.
CR1 to connector J1 pins 3, 9, 12.
c.  Oscillator Circuit. The crystal oscillator consists
f.  Power-On Delay. When the system input circuit
of transistors Q1 and Q2 and crystal X1. Transistors Q1
breaker is closed, +120 vdc input voltage is applied to
and Q2 operate as a relaxation oscillator. The 15.36-kHz
connector J1 pin 2 and thus to power-on delay circuit U6,
output to the frequency divider is buffered by U1.
R22 and C23. When +120 vdc is first applied, U6-3 is
d. Frequency Divider Circuit. The frequency divider
held at 5 vdc and Q7 is off until capacitor C23 charges
consists of divide-by-16 counters U2 and U3. The output
through resistor R22. When the charge on capacitor C22
to the SCR driver is a 60-Hz square wave through
exceeds approximately 3.5 volts, U6-3 goes to zero,
connector J2, pin 2.
which turns Q7 off.  This delay is approximately 2
seconds after turn-on of the inverter input circuit breaker.
e. SCR Driver.
When transistor Q7 turns off, U7-5 goes high and on the
(1)  Nonparallel SCR driver input.  When the
next 120-Hz clock from Q8 U3-8, U7-6 goes high. When
inverter is operated as a single unit (nonparallel), jumpers
U7-6 goes high, U44 and -9 go high and the inverter drive
are connected across connector P2 which plugs into
from U3-11 is applied to Q4 and Q5.
connector J2. The jumpers in connector P2 are from pin
g. Sensor Delay.  The sensor delay consists of
7 to 8, 3 to 10, 2 to 11, and 6 to 12. No other connections
transistor Q10.  During the 2-second power-on delay,
are made to connector P2 in the nonparallel mode. Thus,
transistor Q10 is held on by U6-3 and capacitor C28
the SCR driver circuit is operated from its own oscillator
charges through resistor R42. The
and frequency divider.
Change 1

Privacy Statement - Press Release - Copyright Information. - Contact Us

Integrated Publishing, Inc.
6230 Stone Rd, Unit Q Port Richey, FL 34668

Phone For Parts Inquiries: (727) 493-0744
Google +