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TM 11-6125-259-30
above). In addition, the original low at the collector
buffered by six inverting amplifiers Z610 and six
of Q604 also causes turn-off of transistor Q608
inverting amplifiers Z609 and the final six logic
putting a low at collector of transistor Q608. this
outputs go to A4A1 board (fig. FO 2-2, sheet 3)
goes to figure FO 2-2,
low at schematic point
through schematic points  through . . .For the
sheet 3, where it turns off transistors Q50 and
minor bridge signals, the three outputs of prom
Q505 thus holding off the +5 vdc supply until the
Z602-4, -5, -6 are fed to nand gates Z603-1, Z603-4
+15 vdc supply has reached at least 13 volts.
and Z603-9 and also directly to inverter amplifiers
Z611-3, Z611-9 and Z811-13 for an inverted out-
Another end result of transistor Q608 turning on
until the +15 vdc supply is proper is that the low at
put. All six logic signals are amplified and buffered
collector of transistor Q608 goes through diode
by inverting amplifiers; three by the original in-
CR612 add resets the latch circuit by setting nand
verting amplifiers Z611-3, Z611-9 and Z611-13 and
gate output Z605-5 to high which sets latch output
the other three by inverting amplifiers Z611-1,
Z605-6 to low; thus preparing circuit for detection
Z611-5 and Z611-11. Note that in the case of an
of possible overcurrent condition.
output overcurrent condition, prom Z602 is
e. Drive Logic.
programmmed for the first five seconds by a low at
input pin 14 to cause a special waveform output at
(1) 9.6 kHz oscillator. The drive logic is con-
trolled by a 9.6 kHz oscillator (fig. FO 2-2, sheet 2)
output pins 1 through 6 so that the inverter output
consisting of transistors Q600 through Q603 and
goes to low voltage and accepts high current flow.
associated components. Initially, tranistor Q600
In the case of an input or 37 vdc supply overvoltage
will be turned off and the remaining transistors will
condition or during initial turnon, prom ZZ602 pin 15
be turned on. With transistor Q602 conducting, a
chip enable input is turned off by a high and, thus,
positive voltage will be coupled through diode
all major and minor bridge logic signals are set to
CR601 and through set-in test resistors R60 and
low, turning off the inverter output.
f. Major and Minor Drive and Bridge Converter,
R607 to charge up capacitor C601. The charge on
capacitor C601 turns on transistor Q600 which
The major bridge consists of transistors Q200
causes transistor Q601 emitter to be more positive
through Q205 and diodes CR200 through CR205
than its base which turns off transistor Q601. This
(fig. FO 2-2, sheet 3). The minor bridge consists of
in turn puts a high at the base of transistor Q602
transistors Q300 through Q305 and diodes CR300
and turns it off. Transistor Q603 is not turned off
through CR305. Both circuits function in a similar
and its collector potential goes high. At the same
manner with the exception of timing an power-
time the charge voltage for capacitor C601 is no
level differences. Schematic points
are the inputs from the logic circuits that control
longer at the anode of diode CR601 and the
capacitor will start to discharge through resistors
the major drive section and points
R607, R608 and R609. The discharge will continue
are the inputs from the logic circuits that control
until transistor Q600 is turned off and the cycle
the minor drive section. The major and minor
repeats itself producing a 9.6 kHz square wave at
sections perform the same in theory, the difference
the collector of transistor Q603. The square wave is
being in the power levels and gating sequence. The
divided and programmed by counter Z600 and prom
major and minor sections are divided into three
Z602 to produce the logic gating (at schematic
identical divisions to produce phase A, phase B and
through  )  pulses for the major and
phase C output voltage. However, due to the
minor bridges.
relationship of the logic signals the individual
(2) Output logic drive signals. The 9.6 kHz
phases can only be isolated at the output trans-
formers T1 and T2. The input signals at points
square ave is fed counter Z600 and from there to
prom Z602. The orignal 9.6 kHz wave is counted
are 180 degrees out of phase, likewise,
down and converted into the logic drivo signals for
to  ,
to  ,  to
the major bridge, which exits A6 logic board at
to . This allows only one control
schematic points
(see below for
transistor to conduct at a time which permits
waveform), and the logic drive signals for the minor
current control in the associated transformer. The
bridge, which exits the A6 logic board at schematic
current control produces polarity changes in the
points  through  . For the major bridge
secondary, which gates associated transistors,
which then determines whether the output trans-
signals, the three outposts of prom Z602-1, -2, -3
are fed to nand gates Z603-13, Z607-5 and Z607-13
former has current flowing or not and if so in what
where each signal is given a second, inverted, output
direction. The waveshapes shown in figure 2-4
line through nand gate Z607-2, Z607-10 and
represent the inputs from the logic circuits to the
Z608-10. The six logic signals are amplified and
major drive section.

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