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Page Title: Static Inverter Circuit Description - continued
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TM 11-6125-259-30
Q701 which as described above, sends current
impedance to ground to the center tap of chokes
L201 and L301. This cuts off all high energy
from the 15 volts through transformers T201
and T301 causing power switch transistors
charging of chokes L201 and L301 and thus all high
energy charging of capacitors C401A and C401B to
Q206, Q207, Q208, Q306, Q307, Q308 to be
37 volts. However, capacitors C401A and C401B are
turned off and thus chokes L201 and L301 are
still able to charge up to the level of the inverter
not being shorted to ground. This is the only
input voltage through the path of input chokes L201
portion of the cycle of operation that both
and L301 and diodes CR307 and CR207. It is this
chokes are in the discharge mode. In the next
cycle of operation the opposite choke will be
input voltage level that is used to produce the +15
shorted to ground.
vdc supply which is still required for the over-
voltage sense circuit so that when an overvoltage
The low at comparator Z703-D output also
condition is no longer present, full operation of the
sets nand gate Z701 output pin 8 to low which
inverter will be restored.
discharges capacitor C704 preparing it be
c. Overcurrent Sense. A, B and C output
charged up during next cycle.
current is monitored by current transformers T500
b. Overvoltage Sense. When the input voltage or
through T502 (fig. FO 2-2, sheet 3). An ac voltage
the +37 vdc supply of the inverter reaches a high of
proportional to the current is present at load
44 volts, the inverter is programmed to shut itself
resistors R500 through R502 and this voltage is
down in order to protect components and to limit
rectified by diodes CR500 through CR505 and the
excess output AC voltage. The overvoltage sense
dc voltage is sent to the overcurrent sense logic
circuit receives the unit input voltage at the anode
circuit (fig. FO 2-2, sheet 2). The Varying dc voltage
of diode CR604 (fig. FO 2-2, sheet 2) and the +37
is made more smooth through resistor R626 and
vdc regulated voltage at the anode of diode CR605.
capacitor C607 and then fed to comparator Z601-5
The hgher (more positive) of the two voltages will
positive input. An overcurrent condition will cause
be present at the cathode of diodes CR604 and
the Z601-5 input to exceed the zener diode CR603
CR605. When the higher voltage reaches 44 volts
reference vltage input at comparator Z601-4
than zener diode CR606 will break down causing
negative input. This drives output Z601-2 to high.
transisstor Q605 to turn on. The resulting low at the
Comparator Z601-1 output, however, is set to low
Collector of Q605 has the following effects:
by an overcurrent condition because the dc error
(1) The output of logic nand gate Z603 pins 3,
voltage in this case goes to Z601-6 negative input.
6 and 8 are set high which causes the minor drive
The low at comparator Z601-1 output goes to prom
output logic points Z611 pins 2, 6 and 10 to shut off
Z602-14 input and programs the major bridge logic
by being held at low.
for low voltage and high current rather than the
(2)Nand gate Z608 input pin 2 is set low which
normal quasi sine waveform. The minor bridge is
Sets nand gate Z608 output pin 6 to low, resulting in
programmed for the quasi sine waveform. The in-
nand gate input Z608 pin 9, Z607 pins 12, 9 ,4, 1 and
verter output will now be able to conduct a high
Z 603 pin 12 being set low which causes the major
level of current for the next 5 seconds until further
drive output logic Z610 pins 2, 4, 6 and Z609 pins 2,
logic (described below) turns off all major bridge
4, 6 to shut off by being held atlow.
logic outputs  through
(3) Nand gate input Z608-12 is set low which
The overcurrent high at comparator Z601-2 output
puts a high at prom Z602-2 chip enable input, thus
allows capacitor C606 to charge to a high which
setting prom output pins 1 though 6 to low, this
turns off all major and minor bridge logic outputs.
triggers timer Z606. This causes timer Z606-4
output to produce a momentary low pulse five
(4) The low at collector of transistor Q605 at
schematic point
seconds after input Z606-10 went high. The
goes into figure FO 2-2, sheet
momentary low at Z606-4 sets nand gate Z605-6
1, where it disables the +37 vdc boost regulation
output to high. This high is at nand gate Z605-2
input and since other input Z606-1 is normally high,
In detail, nand gate Z701 input pin 12 (fig. FO 2-2,
then Z605-3 output goes low causing Z605-6
sheet 1) is set low causes transistor Q705 to
output to latch at high. The latched high goes to
turn on causing a low at comparator Z703-B input
nand gate Z605-12 input and since other input
pin 11. This low removes the effect of zener diode
Z605-13 is at high due to overcurrent condition,
CR707 and sets Z703-B output low which sets
output Z605-11 is set to low. The high-low tran-
comparator Z703-C output low which sets com-
sition at Z605-11 output triggers timer Z604-1
parator Z703-D output low which finally turns off
input which cause a 1.5 second positive ulse at
all power switch transistors Q206, Q207, Q208,
timer output Z604-13 (the negative pulse at timer
Q306, Q307, and Q308, thus removing the low

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